The invention relates to a data output buffer for use in a semiconductor device and in particular the data output buffer for precharging a data bus prior to outputting actual data in a semiconductor device using an address transition detection (ATD) circuit.
In general, a data output buffer of a static random access memory (SRAM) provides an output in response to a READ/WRITE control signal, wherein outputs SAS,SAS of a differential amplifier stage in a sense amplifier are initially kept in an intermediate level (that is, precharge state) between logic HIGH state and logic LOW state, and then chosen into either one of the logic HIGH or LOW states when data comes out from the memory cell.
Referring to FIG. 1 illustrating a schematic circuit diagram of a prior-art data output buffer without any data precharging means, an output SAQ of a differential amplifier stage is coupled to each input of NAND gate A11 and NOR gate O11 whose other inputs are respectively coupled to an output enable signal OE, an inverter I11 being connected between said other inputs of the NAND gate and the NOR gate. Thus, the output SAQ of the differential amplifier stage is delivered, in response to the output enable signal, to PMOS transistor T11 and NMOS transistor T12 through the NAND gate and the NOR gate, and inverters INV12 to INV15, thereby providing the buffered data to an I/O pad coupled to the PMOS and NMOS transistors. Said output buffer circuit without a data precharging means generally requires a long swing time in its operation, because the output voltage of the I/O pad swings with a great amplitude when it sequentially reads out the data of contrary logic state, more than at least two times, the output voltage of said I/O pad being continuously transferred into a logic LOW state from a logic HIGH state and then vice versa. Consequently, the prolonged access time and the noise in source supplying voltages such as, for example, Vcc and Vss, resulting from a transient peak current according to the swing width, lead to malfunction of the entire chip operation.
To remedy the above mentioned problem, another prior-art data output buffer has been disclosed in an article titled "A 34 ns 1 Mb CMOS SRAM using Triple Poly" of Tomohisa et al. in the page 262-263, a February 1987 issue of IEEE International Solid-State Circuits Conference (ISSCC), wherein there is shown a method concerning a data output buffer having therein a precharging circuit, as illustrated in FIG. 2.
FIG. 3 is a timing diagram showing every aspect of operations according to the circuit of FIG. 2. When an input SAQ is sequentially changed as "HIGH.fwdarw.1/2 Vcc.fwdarw.LOW" and then "LOW.fwdarw.1/2 Vcc.fwdarw.HIGH", the logic states at nodes 21, 22 are respectively changed as "HIGH.fwdarw.LOW" and then "LOW.fwdarw.HIGH" by the difference to input trip levels in inverters I21 and I22, thereby a HIGH pulse of node 25 precharging the input/output bus (I/O bus). However, the sizes of NMOS transistor T21 and PMOS transistor T22 should be comparatively large to make the precharging of data within a very short period of time. Because this large size leads to the formation of a DC current path through P-channel transistor of NAND gate A21, and also N-channel transistor of MOS transistors T21, T22 and NOR gate O22, a problem arises that the current consumption of a precharging driver itself increases. Furthermore, as the node 26 falls below the Vcc voltage level and the node 28 rises above the Vss voltage level, the data output drivers T23, T24 turn ON, thereby making another DC current path. Also, as the two inverters I21, I22 sharing a single input provide the outputs of logic HIGH and LOW, respectively, by the difference in their input trip levels, with the outputs precharging the data bus, the precharging time greatly changes in case that the input trip level of the inverters changes according to the process variation thereof. In the worst case, this results in the malfunction of the entire chip.